The present invention relates generally to a MOS transistor circuit, and particularly to the MOS transistor circuit for use as input register of an ALU (arithmetic logic unit) of a micro-processor. The input register is for holding a signal of one selected bus among signals of plural internal bus lines and outputs to feed to the ALU. FIG. 1 shows a conventional configuration of input register A and related circuits, and FIG. 2 shows wave forms of various parts of FIG. 1. Data bus lines DB.sub.0, DB.sub.1, DB.sub.2 and DB.sub.3 are each for bit data bus, and signals thereon are designated as b, c, d and e, respectively.
The circuit part A is the part that which is improved by the present invention, wherein a known complex gate constituted by plural CMOS logic gates operates in such a manner that any one of the signals b, c, d and e selectively issued as inverted output signal K responding to selection signal SEL.sub.0, SEL.sub.1, SEL.sub.2 or SEL.sub.3 being at L level. That is, the complex gate 13 operates as a data selector. A block B is a known data latch, in which when enable (ENB) signal j is at a high level (hereinafter is referred as H level) input signal k is inverted and issued as output signal 1 at its data output signal terminal DATA. When ENB signal j is at L-level, it latches input signal k at the input terminal at the time of transition of the signal j from H-level to L-level. The circuit comprises p channel FETs 16, 17, 18 and 19 and n channel FETs 20, 21, 22 and 23. Four p channel FETs 1, 2, 3 and 4 are provided for precharging data bus lines DB.sub.0, DB.sub.1, DB.sub.2 and DB.sub.3, respectively, and the data bus lines are precharged to power supply voltage V.sub.DD when precharge signal PCH is applied to the gates of the p channel transistors 1, 2, 3 and 4. Ihe data bus lines DB.sub.0, DB.sub.1, DB.sub.2 and DB.sub.3 have load capacitances 5, 6, 7 and 8, respectively. Registers 9, 10, 11 and 12 are connected by their output terminals to the data bus lines DB.sub.0, DB.sub.1, DB.sub.2 and DB.sub.3, respectively, and are each constituted the same as each other, each having an n channel transistor 90 whose drain is connected to the bus line. The output terminal DATA of the input register A is connected to an input terminal of subsequently connected (not shown) ALU (arithmetic logic unit).
Operation of the conventional circuit configuration shown in FIG. 1 is elucidated. As shown in FIG. 2, the circuits of micro-processor including the data bus lines DB.sub.0, DB.sub.1, DB.sub.2 and DB.sub.3 and the ALU (not shown) are working in synchronism with clock signals of four phases T1, T2, T3 and T4. Firstly, at the timings of T1 and T3, valid data are impressed on data bus lines DB.sub.0, DB.sub.1, DB.sub.2 and DB.sub.3, and the prechargings of the data bus lines are carried out in the timings T2 and T4 as shown in curve a of FIG. 2 whereon the precharge signal PCH is at L level at T2 and T4. And, the timing when the subsequent ALU comes into processing operation is the timing of T4. That is, the input register A selectively reads either one of the data bus signal b, c, d or e at the timing of T3, and the read-in signal should be fed to the ALU as soon as possible.
As shown by wave forms f, g, h, i and j of FIG. 2, the selection signals SEL.sub.0 through SEL.sub.3 and enable signal ENB are fed at the timing of beginning part of the time T3. Accordingly at the beginning part of T3, output transistors of the registers 10 and 12 becomes ON, and accordingly data signal "H", "L", "H" and "L" are impressed on the data bus lines DB.sub.0, DB.sub.1, DB.sub.2 and DB.sub.3, respectively. Since these data bus lines DB.sub.0 through DB.sub.3 have load capacitance 5, 6, 7 and 8, transitions from H-level (voltage V.sub.DD of power supply) to L level (ground level) take some finite time, that is the level does not decrease rapidly enough. Accordingly, rising of signal on the bus DB.sub.1 selected by the signal SEL.sub.1 from L-level to V.sub.DD /2 (.apprxeq.5V/2=2.5 V) which is the circuit threshold voltage of the CMOS complex gates requires a propagation delay t.sub.1 as shown in curve form c of FIG. 2. Therefore, from the time of entering the time phase T3 to the transistion of the L-signal of data bus DB.sub.1 to output terminal DATA of the input register A takes a considerable time t.sub.A. Therefore, the arrival of the signal to the subsequent ALU (not shown) from the data bus is considerably delayed. Furthermore, the input register A comprises 16 transistors in complex gate 13 and 12 transistors in data latch part B, that is 28 transistors in total in the input register A. This number of transistors in this circuit only represents a single bit data latching. As a conclusion, there are too many transistors comprised in the input register A. For instance, in a case of an input register for a 16-bit ALU, where the input register must latch 32-bit data, the number of transistors to be contained in the input register becomes such a large number as 896 (=28.times.32) and they occupy a large area on the integrated circuit. Therefore, a more simply configurated input register has been envisaged.